A Probabilistic Neural Network Hardware System
Using A Learning-Parameter Paralell Architecture
Noriyuki Aibe, Moritoshi Yasunaga, Ikuo Yoshihara, and Jung H Kim.
| Abstract |
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A novel PNN (Probabilistic Neural Networks) hardware
architecture called `Sigma Parallel Architecture' (SPA) is
proposed. Different values of the network parameter are caluculated in
parallel in the SPA and it speeds up the PNN learning as well
as recognition overcoming the difficulty in the VLSI
implementation. The hardware prototype is developed using FPGA chips and it
shows a high speed leaning of about 10 seconds
that satisfies the requirements in the real world image
recognition tasks.
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